ACTS541T
Die Characteristics
DIE DIMENSIONS:
(2600µm x 2600µm x 533µm
±51µm)
102 x 102 x 21mils
±2mil
METALLIZATION:
Type: Al Si Cu
Thickness: 10.0k
Å
±2k
Å
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire)
Bond Pad #20 (V
CC
) First
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 8.0k
Å
±1.0k
Å
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
182
PROCESS:
CMOS SOS
Metallization Mask Layout
ACTS541T
(19) OE2
(20) V
CC
(1) OE1
(18) YO
(3) A1
(2) A0
A2 (4)
(17) Y1
A3 (5)
(16) Y2
NC
NC
NC
NC
A4 (6)
(15) Y3
A5 (7)
(14) Y4
Y7 (11)
Y6 (12)
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
3
GND (10)
Y5 (13)
A6 (8)
A7 (9)
INTERSIL [ INTERSIL CORPORATION ]
