Specifications HS-80C85RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
(NOTE 1)
PARAMETER
Input Capacitance
SYMBOL
CIN
CONDITIONS
VDD = Open, f = 1MHz
VDD = Open, f = 1MHz
VDD = Open, f = 1MHz
TEMPERATURE
MIN
MAX
12
UNITS
pF
o
T = +25 C
-
-
-
A
o
I/O Capacitance
Output Capacitance
NOTE:
CI/O
T = +25 C
13
pF
A
o
COUT
T = +25 C
12
pF
A
1. All measurements referenced to device ground.
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE: The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2.
o
TABLE 5. BURN-IN DELTA PARAMETERS (+25 C; In Accordance With SMD)
TABLE 6. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY
ADDRESS BRANCHED TO (1)
NAME
PRIORITY
WHEN INTERRUPT OCCURS
TYPE TRIGGER
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
1
2
3
4
5
24H
3CH
Rising edge and high level until sampled.
Rising edge (latched)
34CH
High level until sampled.
2CH
High level until sampled.
See Note 2
High level until sampled.
NOTES:
1. The processor pushes the PC on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.
TABLE 7. BUS TIMING SPECIFICATION AS A t
DEPENDENT
CYC
SYMBOL
tAL
HS-8OC85RH
(1/2)T- 175
SYMBOL
tCC
HS-8OC85RH
Minimum
Minimum
Minimum
Minimum
Minimum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
(3/2 + N)T - 175
(1/2)T - 190
(3/2)T - 500
(1/2)T - 160
(1/2)T +125
(1/2)T +125
(2/2)T - 200
(1/2)T-210
Minimum
tLA
(1/2)T- 175
tCL
Minimum
Maximum
Minimum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
Maximum
tLL
(1/2)T-50
tARY
tHACK
tHABF
tHABE
tAC
tLCK
tLC
(1/2)T- 125
(1/2)T- 100
tAD
(5/2 + N)T - 375
(3/2 + N)T - 375
(1/2)T- 130
tRD
tRAE
tCA
t1
(1/2)T - 100
(3/2 + N)T - 175
(1/2)T-100
t2
(1/2)T- 150
(3/2)T - 200
(4/2)T - 325
tDW
tWD
tRV
tLDR
NOTE: N is equal to the total WAIT states T = tCYC
Spec Number 518054
7
INTERSIL [ Intersil ]
