HS-80C85RH
2. A 10MΩ resistor is required between X1 and X2 for bias point
INSIDE THE
80C85RH
EXTERNAL
stabilization. In addition, the crystal should have the following
characteristics:
TRAP
INTERRUPT
REQUEST
TRAP
1) Parallel resonance at twice the desired internal clock
frequency
TRAP
RESET IN
SCHMITT
TRIGGER
RESET
2) CL (load capacitance) ≤ 30pF
3) CS (shunt capacitance) ≤ 7pF
4) RS (equivalent shunt resistance) ≤ 75Ω
5) Drive level: 10mW
INTERRUPT
REQUEST
CLK
D
VDD
Q
D
F/F
CLEAR
6) Frequency tolerance: ±0.005% (suggested)
TRAP F.F.
INTERNAL
TRAP
ACKNOWLEDGE
A parallel-resonant LC circuit may be used as the frequency-
determining network for the HS-80C85RH, providing that its
frequency tolerance of approximately ±10% is acceptable.
The components are chosen from the formula:
FIGURE 8. TRAP AND RESET IN CIRCUIT
The TRAP interrupt is special in that is disables interrupts,
but preserves the previous interrupt enable status. Perform-
ing the first RIM instruction following a TRAP interrupt allows
you to determine whether interrupts were enabled or
disabled prior to the TRAP. All subsequent RIM instructions
provide current interrupt enable status. Performing a RIM
instruction following INTR, or RST 5.5-7.5 will provide
current interrupt enable status, revealing that interrupts are
disabled.
1
f =
2π√ L (Cext + Cint)
To minimize variations in frequency, it is recommended that
you choose a value for Cext that is at least twice that of Cint,
or 30pF. The use of an LC circuit is not recommended for
frequencies higher than approximately 4MHz.
An RC circuit may be used as the frequency-determining
network for the HS-80C85RH if maintaining a precise clock
frequency is of no importance. Variations in the on-chip tim-
ing generation can cause a wide variation in frequency when
using the RC mode. Its advantage is its low component cost.
The driving frequency generated by the circuit shown is
approximately 3MHz. It is not recommended that frequen-
cies greatly higher or lower than this be attempted.
The serial I/O system is also controlled by the RIM and SIM
instructions. SID is read by RIM, and SIM sets the SOD
data.
Driving the X1 and X2 Inputs
You may drive the clock inputs of the HS-80C85RH with a
crystal, an LC tuned circuit, an RC network, or an external
clock source. The driving frequency may be any value from
DC to 4MHz and must be twice the desired internal clock
frequency.
Figure 9 shows the recommended clock driver circuits.
For driving frequencies up to and including 4MHz you may
supply the driving signal to X1 and leave X2 open-circuited
(Figure 9D).
The following guidelines should be observed when a crystal
is used to drive the HS-80C85RH clock input:
1. A 20pF capacitor should be connected from X2 to ground to
assure oscillator start-up at the correct frequency.
80C85RH
80C85RH
X1
X1
X2
1
1
2
20pF
REXT =
10MΩ
CINT =
15pF
-6K
2
20pF
X2
a.) QUARTZ CRYSTAL CLOCK DRIVER
c.) RC CIRCUIT CLOCK DRIVER
LOW TIME > 60ns
X1
80C85RH
X1
1
CINT =
15pF
LEXT
CEXT
X2
2
†
X2
† X2 Left Floating
b.) LC TUNED CIRCUIT CLOCK DRIVER
d.) 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK DRIVER
CIRCUIT
FIGURE 9. CLOCK DRIVER CIRCUITS
Spec Number 518054
13
INTERSIL [ Intersil ]
