HS-82C55ARH
Waveforms
TRLRH
RD
TPVRL
INPUT
TAVRL
CS, A1, A0
TRHAX
CS, A1, A0
TRHPX
D7 - D0
TAVWL
TWHAX
WR
TDVWH
TWHDX
TWLWH
D7 - D0
TRLDV
TRHDZ
OUTPUT
TWHPV
FIGURE 1. MODE 0 (BASIC INPUT)
FIGURE 2. MODE 0 (BASIC OUTPUT)
TWHOL
TSLSH
STB
WR
TKLOH
IBF
TSLIH
TRHIL
INTR
TSHNH
RD
TSHPX
INPUT FROM
PERIPHERAL
TPVSH
OUTPUT
TWHPV
ACK
TKLKH
TKHNH
INTR
TWLNL
OBF
TRLNL
FIGURE 3. MODE 1 (STROBED INPUT)
FIGURE 4. MODE 1 (STROBED OUTPUT)
DATA FROM CPU
TO HS-82C55ARH
WR
TKLOH
OBF
TWHOL
INTR
ACK
TSLSH
STB
TKLKH
A0 - A1, CS
TAVWL
DATA BUS
TDVWH
TWHDX
WR
TWLWH
TWHAX
FIGURE 6. WRITE TIMING
IBF
TSLIH
TKLPV
TPVSH
PERIPHERAL
BUS
RD
DATA FROM PERI-
PHERAL TO
HS-82C55ARH
TKHPX
A0 - A1, CS
TAVRL
TSHPX
DATA FROM
HS-82C55ARH
TO PERIPHERAL
TRHIL
RD
TRHDX
DATA FROM
HS-82C55ARH
TO CPU
TAVRL
DATA BUS
HIGH IMPEDANCE
VALID
HIGH IMPEDANCE
TRLRH
TRHAX
FIGURE 5. MODE 2 (BIDIRECTIONAL)
NOTE: Any sequence where WR occurs before ACK and STB
occurs before RD is permissible.
FIGURE 7. READ TIMING
4
INTERSIL [ INTERSIL CORPORATION ]
