HS-82C55ARH
Mode 0 Configurations (Continued)
CONTROL WORD #12
CONTROL WORD #13
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
8
4
4
8
8
4
4
8
A
C
B
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
A
C
B
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 - D0
D7 - D0
CONTROL WORD #14
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
8
4
4
8
8
4
4
8
A
C
B
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
A
C
B
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 - D0
D7 - D0
INTR (Interrupt Request)
Operating Modes
A “high” on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the rising edge of STB and reset by the falling edge of RD.
This procedure allows an input device to request service
from the CPU by simply strobing its data into the port.
Mode 1 (Strobed Input/Output)
This functional configuration provides a means for
transferring I/O data to or from a specified port in conjunction
with strobes or “handshaking” signals. In Mode 1, Port A and
Port B use the lines on Port C to generate or accept these
“handshaking” signals.
INTE A
Controlled by Bit Set/Reset of PC4.
Mode 1 Basic Functional Definitions:
• Two Groups (Group A and Group B)
INTE B
Controlled by Bit Set/Reset of PC2.
• Each group contains one 8-bit port and one 4-bit
control/data port.
MODE 1 (PORT A)
CONTROL WORD
MODE 1 (PORT B)
CONTROL WORD
• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1/0
1
1
1
• The 4-bit port is used for control and status of the 8-bit
port.
PC6, 7
1 = INPUT
0 = OUTPUT
Input Control Signal Definition
PA7 - PA0
INTE
PB7 - PB0
INTE
8
8
STB (Strobe Input)
STB
A
STB
B
PC4
PC2
A
B
A “low” on this input loads data into the input latch.
PC5
PC1
IBF
A
IBF
B
IBF (Input Buffer Full F/F)
RD
RD
A “high” on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgment.
IBF is set by STB input being low and is reset by the rising
edge of the RD input.
PC3
INTR
A
PC0
INTR
B
2
PC6, 7
I/O
FIGURE 15. MODE 1 INPUT
12
INTERSIL [ Intersil ]
