HS-82C08RH
Pinouts
20 LEAD CERAMIC DUAL-IN-LINEMETAL-SEAL PACKAGE
(SBDIP) MIL-STD-1835, CDIP2-T20
TOP VIEW
A0
A1
A2
A3
A4
A5
A6
A7
OE
1
2
3
4
5
6
7
8
9
20 V
DD
19 B0
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 T/R
20 LEAD CERAMIC METAL SEALFLATPACK PACKAGE
(FLATPACK) MIL-STD-1835, CDFP4-F20
TOP VIEW
A0
A1
A2
A3
A4
A5
A6
A7
OE
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
B0
B1
B2
B3
B4
B5
B6
B7
T/R
GND 10
PIN
A0-A7
B0-B7
DESCRIPTION
Local Bus Data I/O Pins
System Bus Data I/O Pins
PIN
T/R
OE
DESCRIPTION
Transmit/Receive Input
Active Low Output Enable
Logic Diagram
A0
1
TSB
TSB
A1
2
TSB
TSB
A2
3
TSB
TSB
A3
4
TSB
TSB
A4
5
TSB
TSB
A5
OE 9
6
B ENABLE
A6
T/R11
A7
8
7
A ENABLE
TSB
TSB
TSB
TSB
12
B7
TSB
TSB
13
B6
14
B5
15
B4
16
B3
17
B2
18
B1
19
B0
NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies to
inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the presence of
regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of these pins with the regenerative
latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-
state condition. A transient drive current of
±1.5mA
at V
DD
/2
±0.5V
for 10ns is required to switch the latch. Thus, CMOS device inputs connected to
the bus are not allowed to float during three-state conditions.
2
INTERSIL [ INTERSIL CORPORATION ]
