ACS521MS
January 1996
Radiation Hardened
8-Bit Magnitude Comparator
Pinouts
20 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20,
LEAD FINISH C
TOP VIEW
GB 1
A0 2
20 VCC
19 YB
18 B7
17 A7
16 B6
15 A6
14 B5
13 A5
12 B4
11 A4
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96709 and Intersil’ QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
-10
Errors/Bit/Day
MEV-cm
2
/mg
B0 3
A1 4
B1 5
A2 6
B2 7
A3 8
B3 9
GND 10
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current
≤
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ)
20 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP4-F20,
LEAD FINISH C
TOP VIEW
GB
A0
B0
A1
B1
A2
B2
A3
B3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
YB
B7
A7
B6
A6
B5
A5
B4
A4
Description
The Intersil ACS521MS is a Radiation Hardened 8 bit magnitude com-
parator device. It provides a low output YB when Word A equals word B
and input GB is low. All other input states cause a high output.
The ACS521MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS521MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9670901VRC
5962F9670901VXC
ACS521D/Sample
ACS521K/Sample
ACS521HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518821
3111.1
INTERSIL [ INTERSIL CORPORATION ]
