ACS161MS
Functional Diagram
SPE
CP
J
CP
K
Q
QN
CD
Q0
P0
MR
J
CP
P1
K
QN
CD
Q
Q1
J
CP
P2
K
Q
QN
CD
Q2
J
CP
K
P3
Q
QN
CD
Q3
PE
TC
TE
TRUTH TABLE
INPUTS
OPERATING MODE
Reset (Clear)
Parallel Load
MR
L
H
H
Count
Inhibit
H
H
H
X
X
CP
X
PE
X
X
X
h
I (Note 2)
X
TE
X
X
X
h
X
I (Note 2)
SPE
X
I
I
h (Note 3)
h (Note 3)
h (Note 3)
P
N
X
I
h
X
X
X
OUTPUTS
Q
N
L
L
H
count
q
N
q
N
TC
L
L
(Note 1)
(Note 1)
(Note 1)
L
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low volt-
age level one setup time prior to the Low-to-High clock transition, X = Don’t Care,q = Lower case letters indicate the state of the referenced
output prior to the Low-to-High clock transition,
= Low-to-High Transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
2. The High-to-Low transition of PE or TE should only occur while ZCP is High for conventional operation.
3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation.
4. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
Spec Number
2
518818
INTERSIL [ INTERSIL CORPORATION ]
