HS-26C32RH
Pinouts
HS1-26C32RH
(16 LD SBDIP)
MIL-STD-1835: CDIP2-T16
TOP VIEW
AIN 1
AIN 2
AOUT 3
ENABLE 4
COUT 5
CIN 6
CIN 7
GND 8
16 VDD
15 BIN
14 BIN
13 BOUT
12 ENABLE
11 DOUT
10 DIN
9 DIN
AIN
AIN
AOUT
ENABLE
COUT
CIN
CIN
GND
HS9-26C32RH
(16 LD FLATPACK)
MIL-STD-1835: CDFP4-F16
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
BIN
BIN
BOUT
ENABLE
DOUT
DIN
DIN
Propagation Delay Timing Diagram
Propagation Delay Load Circuit
DUT
TEST
POINT
-V
IN
INPUT
+V
IN
= 0V
t
PLH
V
OH
V
S
= 50%
V
OL
OUTPUT
t
PHL
0V
+2.5V
C
L
R
L
-2.5V
C
L
= 50pF
R
L
= 1000Ω
Three-State Low Timing Diagram
V
IH
V
S
V
SS
t
PZL
V
OZ
V
T
V
OL
OUTPUT
V
W
t
PLZ
INPUT
Three-State High Timing Diagrams
V
IH
V
S
V
SS
t
PZH
V
OH
V
T
V
OZ
OUTPUT
V
W
t
PHZ
INPUT
2
FN3402.4
August 1, 2008