IS-1825ASRH
Die Characteristics
DIE DIMENSIONS:
4310µm x 5840µm (170 mils x 230 mils)
Thickness: 483µm
±
25.4µm (19 mils
±
1 mil)
INTERFACE MATERIALS
Glassivation
Type: Phosphorus Silicon Glass (PSG)
Thickness: 8.0kA +/- 1.0kA
Top Metallization
Type: AlSiCu
Thickness: 16.0kA +/- 2kA
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
585
Metallization Mask Layout
IS-1825ASRH
RT
CT
RAMP
SS
ILIM/SD
OGND
GND
CLK/LEB
E/A OUT
NON-INV
INV
VREF
VCC
OUT A
OUT B
PGND
VC
VC
Notes:
1. Both the OGND (oscillator ground) and the GND (control circuit ground) pads must be bonded to ground.
These pads are both bonded to the GND pin on the packaged devices.
2. All double-sized bond pads must be double bonded for current sharing purposes.
PGND
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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2
FN9065.1
June 14, 2005
INTERSIL [ INTERSIL CORPORATION ]
