82C37A
Figure 7 shows an application for a DMA system using the for A8-A15 from the DMA controller’s data bus is on the local
82C37A DMA controller and the 80C286 Microprocessor.
80C286 address bus so that memory chip selects may still
be generated during DMA transfers. The transceiver on A0-
A7 is controlled by AEN and is not necessary, but may be
used to drive a heavily loaded system address bus during
transfers. The data bus transceivers simply isolate the DMA
controller from the local microprocessor bus and allow pro-
gramming on the upper or lower half of the data bus.
In this application, the system clock comes from the 82C284
clock generator PCLK signal which is inverted to provide
proper READY setup and hold times to the DMA controller in
an 80C286 system. The Read and Write signals from the
DMA controller may be wired directly to the Read/Write con-
trol signals from the 82C288 Bus Controller. The octal latch
CHIP SELECT
TO MEMORY/
PERIPHERALS
LATCH
DECODE
80C286
A0-A23
A0 - A23
MEMR
MEMW
MEMORY
SYSTEM
BUS
TRANSCEIVER
MEMCS
D0-D15
D0 - D15
READY
IOR
IOW
HLD
I/O
DEVICE
HLDA
CLK
DREQ
CS
LATCH
STB
TRANSCEIVER
TRANS-
CEIVER
TRANS-
CEIVER
DACK
T/R
OE
82C288
OE
IORC
IOWC
IOR
IOW
AEN
MRDC
MWTC
MEMR
MEMW
D0-D7
V
CC
CLK
82C284
CLK
AEN
ADSTB
HRQ
HLDA
CLK
EOP D0-D7
82C37A
A0-A7
IOR
IOW
MEMR
MEMW
IOR
IOW
MEMR
MEMW
TO CORRESPONDING
82C288 SIGNALS AND
MEMORY/PERIPHERALS
PCLK
READY
DREQ 0-3
DACK 0-3
READY
FIGURE 7. 80C286 DMA APPLICATION
4-204
INTERSIL [ Intersil ]
