欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-0620702Q3A 参数 Datasheet PDF下载

5962-0620702Q3A图片预览
型号: 5962-0620702Q3A
PDF下载: 下载PDF文件 查看货源
内容描述: 【 15kV ESD保护, + 3.3V , 1Microamp , 250kbps的, RS - 232发射器/接收器 [【15kV ESD Protected, +3.3V, 1Microamp, 250kbps, RS-232 Transmitters/Receivers]
分类和应用: 驱动器接口集成电路
文件页数/大小: 9 页 / 195 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
 浏览型号5962-0620702Q3A的Datasheet PDF文件第1页浏览型号5962-0620702Q3A的Datasheet PDF文件第2页浏览型号5962-0620702Q3A的Datasheet PDF文件第3页浏览型号5962-0620702Q3A的Datasheet PDF文件第4页浏览型号5962-0620702Q3A的Datasheet PDF文件第5页浏览型号5962-0620702Q3A的Datasheet PDF文件第6页浏览型号5962-0620702Q3A的Datasheet PDF文件第7页浏览型号5962-0620702Q3A的Datasheet PDF文件第8页  
5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A
Ceramic Leadless Chip Carrier Packages (CLCC)
0.010 S E H S
D
D3
J20.A
MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
INCHES
SYMBOL
A
A1
B
B1
B2
B3
D
D1
D2
MIN
0.060
0.050
-
0.022
0.006
0.342
MAX
0.100
0.088
-
0.028
0.022
0.358
MILLIMETERS
MIN
1.52
1.27
-
0.56
0.15
8.69
1.83 REF
0.56
9.09
MAX
2.54
2.23
-
0.71
NOTES
6, 7
-
-
2, 4
-
-
-
-
-
2
-
-
-
2
-
-
2
5
5
-
-
-
-
3
3
3
Rev. 0 5/18/94
j
x 45
o
B
E3
E
0.072 REF
0.200 BSC
0.100 BSC
-
0.342
0.358
0.358
-
5.08 BSC
2.54 BSC
9.09
9.09
5.08 BSC
2.54 BSC
-
0.38
1.02 REF
0.51 REF
1.14
1.14
1.91
0.08
5
5
20
1.40
1.40
2.41
0.38
9.09
1.27 BSC
8.69
h x 45
o
0.010 S E F S
A
A1
PLANE 2
PLANE 1
D3
E
E1
E2
E3
e
e1
h
j
0.007 M E F S H S
B1
L
-H-
0.200 BSC
0.100 BSC
-
0.015
0.358
-
0.050 BSC
0.040 REF
0.020 REF
0.045
0.045
0.075
0.003
5
5
20
0.055
0.055
0.095
0.015
-E-
L
L1
L2
L3
ND
NE
N
e
L3
-F-
E1
B3
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
E2
L2
B2
L1
e
1
D1
D2
9
FN6297.0
May 31, 2006