ISL23428
Operating Specifications
SYMBOL
t
DCP
V
CC
= 2.7V to 5.5V, V
LOGIC
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
Wiper Response Time
TEST CONDITIONS
W option; CS rising edge to wiper new
position, from 10% to 90% of final value.
U option; CS rising edge to wiper new
position, from 10% to 90% of final value.
T option; CS rising edge to wiper new
position, from 10% to 90% of final value.
tShdnRec
DCP Recall Time from Shutdown Mode
CS rising edge to wiper recalled position
and RH connection
Ramp monotonic at any level
0.01
MIN
(Note 19)
TYP
(Note 7)
0.4
1.5
3.5
1.5
50
MAX
(Note 19)
UNITS
µs
µs
µs
µs
V/ms
V
CC,
V
LOGIC
V
CC ,
V
LOGIC
Ramp Rate (Note 20)
Ramp
Serial Interface Specification
SYMBOL
V
IL
V
IH
Hysteresis
V
OL
R
pu
PARAMETER
Input LOW Voltage
Input HIGH Voltage
SDI and SCK Input Buffer
Hysteresis
SDO Output Buffer LOW Voltage
SDO Pull-Up Resistor Off-Chip
For SCK, SDI, SDO, CS Unless Otherwise Noted.
TEST CONDITIONS
MIN
(Note 19)
-0.3
0.7 x V
LOGIC
V
LOGIC
> 2V
V
LOGIC
< 2V
I
OL
= 3mA, V
LOGIC
> 2V
I
OL
= 1.5mA, V
LOGIC
< 2V
Maximum is determined by
t
RO
and t
FO
with maximum
bus load Cb = 30pF,
f
SCK
= 5MHz
10
V
LOGIC
= 1.7V to 5.5V
V
LOGIC
= 1.2V to 1.6V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
V
LOGIC
≥
1.7V
200
100
100
250
250
50
50
10
10
0
50
150
0
20
100
5
1
0.05 x V
LOGIC
0.1 x V
LOGIC
0
0.4
0.2 x V
LOGIC
1.5
TYP
(Note 7)
MAX
(Note 19)
0.3 x V
LOGIC
V
LOGIC
+ 0.3
UNITS
V
V
V
V
V
V
kΩ
C
pin
f
SCK
t
CYC
t
WH
t
WL
t
LEAD
t
LAG
t
SU
t
H
t
RI
t
FI
t
DIS
t
SO
t
V
t
HO
SCK, SDO, SDI, CS Pin Capacitance
SCK Frequency
SPI Clock Cycle Time
SPI Clock High Time
SPI Clock Low Time
Lead Time
Lag Time
SDI, SCK and CS Input Setup Time
SDI, SCK and CS Input Hold Time
SDI, SCK and CS Input Rise Time
SDI, SCK and CS Input Fall Time
SDO Output Disable Time
SDO Output Setup Time
SDO Output Valid Time
SDO Output Hold Time
pF
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
FN7904.0
August 25, 2011
INTERSIL [ INTERSIL CORPORATION ]
