ISL23428
the same time, the resistance between RWi and RLi increases
SERIAL DATA OUTPUT (SDO)
monotonically, while the resistance between RHi and RWi
decreases monotonically.
The SDO is a serial data output pin. During a read cycle, the data
bits are shifted out on the falling edge of the serial clock SCK and
will be available to the master on the following rising edge of SCK.
While the ISL23428 is being powered up, both WRi are reset to
40h (64 decimal), which positions RWi at the center between RLi
and RHi.
The output type is configured through ACR[1] bit for Push-Pull or
Open Drain operation. Default setting for this pin is Push-Pull. An
external pull-up resistor is required for Open Drain output
operation. When CS is HIGH, the SDO pin is in tri-state (Z) or
high-tri-state (Hi-Z) depends on the selected configuration.
The WRi can be read or written to directly using the SPI serial
interface, as described in the following sections.
Memory Description
CHIP SELECT (CS)
The ISL23428 contains three volatile 8-bit registers: Wiper Register
WR0, Wiper Register WR1, and Access Control Register (ACR).
Memory map of ISL23428 is shown in Table 1. The Wiper Register
WR0 at address 0 contains current wiper position of DCP0; the
Wiper Register WR1 at address 1 contains current wiper position of
DCP1. The Access Control Register (ACR) at address 10h contains
information and control bits described in Table 2.
CS LOW enables the ISL23428, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power-up. When CS is HIGH, the
ISL23428 is deselected and the SDO pin is at high impedance,
and the device will be in the standby state.
V
LOGIC
TABLE 1. MEMORY MAP
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I C logic source.
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
2
10
1
ACR
WR1
WR0
40
40
40
Principles of Operation
The ISL23428 is an integrated circuit incorporating two DCPs
with its associated registers and an SPI serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
0
6
5
0
4
0
3
0
2
0
1
0
0
NAME/
VALUE
SHDN
SDO
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions.
The SDO bit (ACR[1]) configures type of SDO output pin. The
default value of SDO bit is 0 for Push-Pull output. The SDO pin
can be configured as Open Drain output for some applications. In
this case, an external pull-up resistor is required; reference the
“Serial Interface Specification” on page 7.
Voltage at any DCP pins, RHi, RLi or RWi, should not exceed V
CC
level at any conditions during power-up and normal operation.
The V pin is the terminal for the logic control digital power
LOGIC
source. It should use the same supply as the SPI logic source
which allows reliable communication with a wide range of
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., each DCP is
forced to end-to-end open circuit and each RW shorted to RL
through a 2kΩ serial resistor, as shown in Figure 25. Default value
of the SHDN bit is 1.
microcontrollers and is independent from the V level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
CC
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RHi and RLi pins). The RWi pin of the DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by an 8-bit volatile Wiper Register
(WRi). When the WR of a DCP contains all zeroes
RH
RW
2kΩ
(WRi[7:0] = 00h), its wiper terminal (RWi) is closest to its “Low”
terminal (RLi). When the WRi register of a DCP contains all ones
(WRi[7:0] = 7Fh), its wiper terminal (RWi) is closest to its “High”
terminal (RHi). As the value of the WRi increases from all zeroes
(0) to all ones (127 decimal), the wiper moves monotonically
from the position closest to RLi to the position closest to RHi. At
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
FN7904.0
August 25, 2011
14
INTERSIL [ Intersil ]
