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AFL2812S 参数 Datasheet PDF下载

AFL2812S图片预览
型号: AFL2812S
PDF下载: 下载PDF文件 查看货源
内容描述: 混合高可靠性DC / DC转换器 [HYBRID-HIGH RELIABILITY DC/DC CONVERTER]
分类和应用: 转换器
文件页数/大小: 12 页 / 216 K
品牌: INTERFET [ INTERFET CORPORATION ]
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AFL28XXS Series
Table 1. Nominal Resistance of Cu Wire
Wire Size, AWG
24 Ga
22 Ga
20 Ga
18 Ga
16 Ga
14 Ga
12 Ga
Resistance per ft
25.7 mΩ
16.2 mΩ
10.1 mΩ
6.4 mΩ
4.0 mΩ
2.5 mΩ
1.6 mΩ
Another potential problem resulting from parasitically
induced voltage drop on the input lines is with regard to
the operation of the enable 1 port. The minimum and
maximum operating levels required to operate this port
are specified with respect to the input common return line
at the converter. If a logic signal is generated with respect
to a ‘common’ that is distant from the converter, the effects
of the voltage drop over the return line must be considered
when establishing the worst case TTL switching levels.
These drops will effectively impart a shift to the logic levels.
In Figure VI, it can be seen that referred to system ground,
the voltage on the input return pin is given by
As an example of the effects of parasitic resistance,
consider an AFL2815S operating at full power of 120W.
From the specification sheet, this device has a minimum
efficiency of 83% which represents an input power of more
than 145W. If we consider the case where line voltage is at
its’ minimum of 16V, the steady state input current necessary
for this example will be slightly greater than 9 amperes. If
this device were connected to a voltage source with 10
feet of 20 gauge wire, the round trip (input and return)
would result in 0.2Ω of resistance and 1.8V of drop from the
source to the converter. To assure 16V at the input, a
source closer to 18V would be required. In applications
using the paralleling option, this drop will be multiplied by
the number of paralleled devices. By choosing 14 or 16
gauge wire in this example, the parasitic resistance and
resulting voltage drop will be reduced to 25% or 31% of that
with 20 gauge wire.
e
Rtn
=
I
Rtn
R
P
Therefore, the logic signal level generated in the system
must be capable of a TTL logic high plus sufficient additional
amplitude to overcome
e
Rtn
. When the converter is inhibited,
I
Rtn
diminishes to near zero and
e
Rtn
will then be at system
ground.
Incorporation of a 100µF capacitor at the input terminals is
recommended as compensation for the dynamic effects
of the parasitic resistance of the input cable reacting with
the complex impedance of the converter input, and to
provide an energy reservoir for transient input current
requirements.
Figure VI. Problems of Parasitic Resistance in input Leads
(See text)
R
p
I
in
100
µfd
Vin
e
Rtn
Rtn
Case
e
source
R
p
I
Rtn
System Ground
Enable 1
Sync Out
Sync In
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