28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix B Architecture Block Diagram
DQ0-DQ15
VCCQ
Output Buffer
Input Buffer
Identifier
Register
Status
Register
I/O Logic
CE#
WE#
OE#
RP#
Command
User
Interface
Power
Reduction
Control
Data
Comparator
WP#
A0-A19
Y-Decoder
Y-Gating/Sensing
Write State
Machine
Program/Erase
Voltage Switch
Input Buffer
VPP
Address
Latch
X-Decoder
VCC
GND
Address
Counter
0580-C1
38
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