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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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ISA-to-PC-Card (PCMCIA) Controllers PD6710/22  
bit 5 is 0), system software can determine the cards operating voltage range and then power-up  
the socket and initialize the card (or simply initialize the card if programmed for automatic power-  
on (Power Control register bit 5 is 1and Extension Control 1 register bit 1 is 1)).  
4.1.10  
4.1.11  
Write FIFO  
To increase performance when writing to PC Cards, two, independent, four-word-deep write  
FIFOs are used. Writes to PC Cards will complete without wait states until the FIFO is full.  
Register states should not be changed until the write FIFO is empty.  
Bus Sizing  
The PD67XX incorporates logic to automatically detect its connection to 8- or 16-bit buses. This is  
accomplished by sensing SBHE* input activity. If the SBHE* pin is always high (that is, tied to  
ISA_VCC), the PD67XX operates in 8-bit mode where all transfers occur on the lower data bus,  
bits 7:0. Any occurrence of the SBHE* going low triggers the PD67XX to operate thereafter as a  
16-bit device. 16-bit operation of the PD67XX is properly triggered when the SBHE* input is  
connected to the systems SBHE* signal. When the PD67XX is operating in 16-bit mode, all ISA  
bus transactions are 16-bit whenever possible, even if installed PC cards only support 8-bit  
transfers. In 16-bit mode, the signals SBHE* and SA0 are used to specify the width of the data  
transfer and the location of data on the bus (which byte lane has the data) during 8-bit transfers.  
The possible combinations for SBHE* and SA0 are shown in Table 9 and Table 10  
Table 9. 16-Bit Mode Operation  
16-Bit Mode Transfer Types  
SBHE*  
SA0  
Word  
0
0
1
1
0
1
0
1
Upper Byte/Odd Address  
Low Byte/Even Address  
Not Valid  
.
Table 10. 8-Bit Mode Operation  
8-Bit Mode Transfer Types1  
SA0  
Even Address  
Odd Address  
0
1
1. The SBHE* signal is pulled up. If the SBHE*  
signal remains high, thePD67XX causes all  
transfers to occur on D[7:0] only  
Typically, there are three types of data transfers to and from the PD67XX:  
16-Bit Transfer from 16-Bit Processor — The CPU puts the address on the bus. Then the  
PD67XX identifies the address on the bus as either an 8- or 16-bit transfer. If the transfer is  
identified as 16-bit, the host acknowledges with the appropriate signal, either MEMCS16* or  
IOCS16*. Data is transferred to/from the data bus as a word on both byte lanes.  
8-Bit Transfer from 16-Bit Processor The CPU puts the address on the bus. Then the  
PD67XX identifies the address on the bus as either an 8- or 16-bit transfer. In this case, the  
transfer is identified as an 8-bit transfer. The host queries SA0 and SBHE* to determine the  
Datasheet  
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