PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
4.1.3
PD67XX Functional Blocks
Figure 7. Functional Block Diagram
Per Chip
Per Socket
Control
Address
Socket
WP/-IOIS16
Bus Control
Bus
Interface
Unit
Mapper
and
Offset
Operation
Registers
-WAIT
Socket
Timing Control
Control
Data
Data
Write
FIFO
Synthe-
sizer
Clock
Address
INTR
IRQs
CD1, CD2
BVD, -STSCHG
RDY/-IREQ
Interrupt
Control
V
CC Control
Power Control
VPP Control
4.1.4
Interrupts
The PD67XX provides ten interrupt pins that are labeled with names suggesting their mapping in
the system, though there are no hard requirements specifying the exact mapping. Typically, all ten
interrupt pins should be connected to system interrupt signals to allow maximum flexibility in
programming interrupt routing from the PD67XX.
Classes of Interrupts
The PD67XX supports two classes of interrupts:
• Socket or card interrupts initiated by the PC Card activating its RDY/-IREQ signal
• Management interrupts triggered by changes in PC Card status, including:
— Card insertion or removal
— Battery warning indicator (BVD2) change on a memory-type card
— Battery dead indicator (BVD1) or I/O-type card status change (-STSCHG)
— Ready (RDY) status change on a memory-type card
Either class of interrupts can be routed to any of the ten interrupt pins on the PD67XX.
30
Datasheet
INTEL [ INTEL ]
