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    SPD6722QCCE 参数 Datasheet PDF下载

    SPD6722QCCE图片预览
    型号： SPD6722QCCE
    PDF下载： 下载PDF文件 查看货源
    内容描述： ISA到PC卡（ PCMCIA ）控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
    分类和应用： 总线控制器微控制器和处理器PC
    文件页数/大小： 138 页 / 837 K
    品牌： INTEL [ INTEL ]
     浏览型号SPD6722QCCE的Datasheet PDF文件第130页浏览型号SPD6722QCCE的Datasheet PDF文件第131页浏览型号SPD6722QCCE的Datasheet PDF文件第132页浏览型号SPD6722QCCE的Datasheet PDF文件第133页浏览型号SPD6722QCCE的Datasheet PDF文件第135页浏览型号SPD6722QCCE的Datasheet PDF文件第136页浏览型号SPD6722QCCE的Datasheet PDF文件第137页浏览型号SPD6722QCCE的Datasheet PDF文件第138页  
    Index  
    Symbols  
    +5V 25  
    C
    C_SEL 19  
    Card Detect bits 47  
    Card Detect Change bit 53  
    Card Detect Enable bit 55  
    Card Enable bit 50  
    Numerics  
    5V Core bit 73  
    Card I/O Map 0–1 Address Offset High regis-  
    ters 62  
    Card I/O Map 0–1 Address Offset Low regis-  
    ters 62  
    Card Is I/O bit 52  
    Card Memory Map 0–4 Offset Address High  
    registers 68  
    Card Memory Map 0–4 Offset Address Low  
    registers 67  
    Card Power On bit 48  
    Card Reset* bit 52  
    A
    A[25:0] 20  
    A21 bit 76  
    A22 bit 76  
    A23/VU bit 76  
    A24/M/S* bit 76  
    A25/CSEL bit 76  
    Active-high GPSTB bit 83  
    AEN 17  
    ALE 17  
    ATA Control register 75  
    ATA mode  
    Card Status Change register 52  
    Card Timer Select bits 67  
    -CD[2:1] 22  
    description 88  
    overview 36  
    -CE[2:1] 22  
    pin cross reference 88  
    ATA Mode bit 75  
    Auto Power Clear Disable bit 78  
    Auto-Power bit 50  
    Auto-Size I/O Window 0 bit 58  
    Auto-Size I/O Window 1 bit 59  
    Chip Information register 74  
    Chip Revision register 46  
    CLK 19  
    Command Multiplier Value bits 86  
    Command Prescalar Select bits 86  
    Command Timing 0–1 registers 85  
    conventions  
    bit naming 40  
    numbers and units 11  
    pin naming 14  
    B
    Battery Dead Or Status Change bit 53  
    Battery Dead Or Status Change Enable bit 54  
    Battery Voltage Detect bits 47  
    Battery Warning Change bit 53  
    Battery Warning Enable bit 54  
    bus sizing 35  
    register headings 39  
    D
    D[15:0] 20  
    BVD1/-STSCHG/-RI 23  
    BVD2/-SPKR/-LED 23  
    Bypass Frequency Synthesizer bit 73  
    Data Mask 0–1 register 78  
    Data Mask Select 0–1 bits 78  
    Data register 44  
    Datasheet  
    135  
    Device Index bit 41  
    DMA Enable bits 79  
    DMA mode  
    H
    host access to registers 36  
    description 97  
    overview 36  
    I
    I/O Map 0 Enable bit 57  
    I/O Map 0–1 Start Address High registers 60  
    I/O Map 1 Enable bit 57  
    I/O Window 0 Size bit 58  
    I/O Window 1 Size bit 59  
    I/O Window Control register 58  
    IDE 88  
    DMA Read Cycle timing 116  
    DMA Request timing 119  
    DMA System bit 74  
    DMA Write Cycle timing 118  
    Drive LED Enable bit 73  
    Dual/Single Socket* bit 75  
    Index register 41  
    -INPACK 21  
    E
    Empty Write FIFO bit 72  
    Enable Manage Int bit 51  
    End Address  
    Inpack Enable bit 71  
    Input Clock specification 108  
    Interface ID bits 46  
    Interface Status register 47  
    Interrupt and General Control register 51  
    interrupts 30  
    19:12 bits 66  
    23:20 bits 67  
    7:0 bits 61  
    Extended Data register 77  
    Extended Index register 77  
    Extended Register Index bits 77  
    Extension Control 2 register 83  
    External Data bits 81, 82  
    External Data register 81  
    -INTR 18  
    IOCHRDY 17  
    IOCS16* 17  
    -IOIS16 21  
    IOR* 16  
    -IORD 21  
    IOW* 16  
    -IOWR 21  
    -IREQ 21  
    IRQ[14, 11, 7, 5:3] 18  
    IRQ10 18  
    F
    FIFO Control register 72  
    form factor 1, ??–123  
    functional blocks 30  
    IRQ10 as DRQ, description 32  
    IRQ12 as LED_OUT*, description 31  
    IRQ12/LED_OUT* 18  
    IRQ15 as RI_OUT*, description 31  
    IRQ15 Is RI Out bit 74  
    IRQ15/RI_OUT* 18  
    IRQ9 18  
    IRQ9 as DACK*, description 32  
    ISA bus timing 104  
    ISA_VCC 19  
    G
    general-purpose strobe  
    control 91  
    example implementations 93  
    overview 32  
    suspend mode 94  
    General-Purpose Strobe timing 108  
    GND 25  
    GPSTB 24  
    GPSTB on IOR* bit 83  
    GPSTB on IOW* bit 83  
    136  
    Datasheet  
    PCMCIA 27  
    L
    PD67XX Revision Level bits 75  
    pin descriptions 12–25  
    pin diagram  
    LA[23:17] 16  
    -LED 23  
    LED Activity Enable bit 79  
    LED_OUT* 18  
    144-pin VQFP 13  
    208-pin PQFP or VQFP 14  
    pin usage summary 25  
    power consumption 34  
    Power Control register 48  
    power management 32  
    power-on  
    Low-Power Dynamic mode 32  
    Low-Power Dynamic Mode bit 73  
    M
    Management Interrupt Configuration register  
    54  
    configuration 25  
    setup 38  
    Management IRQ Select bits 55  
    Mapping Enable register 55  
    MEMCS16 Full Decode bit 56  
    MEMCS16* 17  
    Memory Map  
    0 Enable bit 56  
    MEMR* 17  
    Pull-up Control bit 79  
    Pulse Management Interrupt bit 70  
    Pulse Mode Interrupt timing 107  
    Pulse System IRQ bit 71  
    PWRGOOD 17  
    MEMW* 17  
    Misc Control 1 register 70  
    Misc Control 2 register 72  
    R
    RDY/-IREQ 21  
    Ready Change bit 53  
    Ready Enable bit 54  
    Ready/Busy* bit 48  
    Recovery Multiplier Value bits 87  
    Recovery Prescalar Select bits 87  
    Recovery Timing 0–1 registers 86  
    REFRESH* 17  
    N
    Normal Byte Read/Write timing 114  
    O
    Odd Byte timing 115  
    -OE 20  
    -REG 20  
    REG Setting bit 68  
    Register Index bits 41  
    RESET 22  
    Reset timing 107  
    Revision bits 46  
    -RI 23  
    RI_OUT* 18  
    Ring Indicate Enable bit 52  
    ordering information 124  
    P
    package  
    144-pin VQFP 121  
    208-pin PQFP 122  
    208-pin VQFP 123  
    PC Card  
    basics 27  
    S
    bus timing calculations 109  
    Read/Write timing 113  
    socket timing 111  
    timing 36  
    SA[16:0] 16  
    SBHE* 16  
    SD[15:0] 16  
    Datasheet  
    137  
    Setup Multiplier Value bits 84  
    Setup Prescalar Select bit 85  
    Setup Timing 0–1 registers 84  
    SLOT_VCC. See SOCKET_VCC  
    socket  
    Reset 107  
    System Interrupt 107  
    Word I/O Read/Write 112  
    Timing Register Select 0 bit 58  
    Timing Register Select 1 bit 59  
    Totem-pole GPSTB bit 83  
    accessing specific registers 42  
    register per 39  
    Socket Index bit 41  
    socket power features 34  
    SOCKET_VCC 23  
    Speaker Enable bit 71  
    Speaker Is LED Input bit 76  
    -SPKR 23  
    SPKR_OUT*/C_SEL 19  
    -STSCHG 23  
    Super-Suspend mode, description 33  
    Suspend bit 73  
    Suspend mode, description 32  
    System Interrupt timing 107  
    V
    VCC 3.3V bit 70  
    VCC Power bit 50  
    VCC Power Lock bit 78  
    -VCC_3 24  
    -VCC_5 24  
    voltage sense 95–96  
    overview 32  
    VPP Valid bit 48  
    VPP_PGM 24  
    -VPP_VALID 19  
    VPP_VCC 24  
    VPP1 Power bits 50  
    T
    Three-State Bit 7 bit 74  
    timing  
    W
    -WAIT 21  
    DMA Read Cycle 116  
    DMA request 119  
    DMA Write Cycle 118  
    General-Purpose Strobe 108  
    ISA bus 104  
    Normal Byte Read/Write 114  
    Odd Byte 115  
    PC Card bus 109  
    -WE 21  
    Window Data Size bit 65  
    windowing 27  
    Word I/O Read/Write timing 112  
    WP/-IOIS16 21  
    write FIFO 35  
    Write Protect bit 48, 69  
    PC Card Read/Write 113  
    PC Card socket 111  
    Pulse Mode Interrupt 107  
    Z
    ZWS* 18  
    138  
    Datasheet  

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