8XC52/54/58
Test Conditions
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to all devices unless otherwise indicated.
Typ
Symbol
Parameter
Min
Max
Unit
(Note 4)
b
b
b
e b
e b
e b
V
OH1
Output High Voltage
(Port 0 in External Bus Mode)
V
V
V
0.3
0.7
1.5
V
V
V
I
I
I
200 mA
3.2 mA
7.0 mA
CC
CC
CC
OH
OH
OH
I
Logical 0 Input Current
(Ports 1, 2 and 3)
IL
b
g
e
e
50
10
mA
mA
V
V
0.45V
V or V
IL
IN
IN
I
I
Input leakage Current (Port 0)
LI
IH
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
Commercial
TL
b
b
e
650
750
mA
mA
V
2V
IN
Express
RRST
CIO
RST Pulldown Resistor
Pin Capacitance
40
225
KX
@
1 MHz, 25 C
10
pF
§
I
Power Supply Current:
Active Mode
(Note 3)
CC
at 12 MHz (Figure 5)
at 16 MHz
at 24 MHz
15
20
28
35
30
38
56
56
mA
mA
mA
mA
at 33 MHz (8XC5X-33)
Idle Mode
at 12 MHz (Figure 5)
at 16 MHz
at 24 MHz
5
6
7
7
5
5
7.5
9.5
13.5
15
mA
mA
mA
mA
mA
mA
at 33 MHz (8XC5X-33)
Power Down Mode
8XC5X-33
75
50
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and
OL
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the V
address lines are stabilizing.
3. See Figures 6–9 for test conditions. Minimum V
on ALE and PSEN to drop below the 0.9 V specification when the
CC
OH
for Power Down is 2V.
CC
4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and 5V.
5. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
OL
Maximum I per 8-bit portÐ
10mA
OL
Port 0:
Ports 1, 2 and 3:
Maximum total I for all output pins:
26 mA
15 mA
71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater
OL OL
than the listed test conditions.
9
INTEL [ INTEL ]
