3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
B.7
Intel-Specific Extended Query Table
Certain flash features and commands are optional. The Intel-Specific Extended Query table
specifies this and other similar types of information.
Table 27. Primary-Vendor Specific Extended Query
Offset(1)
P = 35h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Addr.
Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
Primary extended query table
35:
36:
37:
38:
39:
3A:
3B:
3C:
3D:
--50
--52
--49
--31
--30
--66
--00
--00
--00
“P”
“R”
“I”
Unique ASCII string “PRI”
1
1
4
Major version number, ASCII
“1”
“0”
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 9–31 are reserved; undefined bits are “0.” If bit 31 is “1” then
another 31 bit field of optional features follows at the end of the bit-30
field.
bit 0 Chip erase supported
bit 0 = 0
No
Yes
Yes
No
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
No
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
Yes
Yes
No
bit 7 Page mode read supported
bit 8 Synchronous read supported
No
Supported functions after suspend: read array, status, query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
(P+9)h
1
2
3E:
--01
bit 0 Program supported after erase suspend
Block status register mask
bit 0 = 1
Yes
(P+A)h
(P+B)h
3F:
40:
--03
--00
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
bit 0 = 1
bit 1 = 1
Yes
Yes
V
logic supply highest performance program/erase voltage
CC
(P+C)h
(P+D)h
1
1
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
41:
--33
--C0
3.3 V
V
optimum program/erase supply voltage
PP
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
42:
12.0 V
Datasheet
57
INTEL [ INTEL ]
