3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 28. Protection Register Information
Offset(1)
P = 35h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Addr.
Value
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
(P+E)h
(P+F)h
1
43:
44:
--01
--80
01
Protection Field 1: Protection Description
80h
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user programmable. Bits 0–15 point
to the Protection register Lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
(P+10)h
45:
--00
00h
4
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC -plane physical high address
bits 16–23 = “n” such that 2n = factory pre- programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+11)h
46:
--03
--03
8 byte
8 byte
(P+12)h
(P+13)h
47:
48:
Reserved for future use
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
58
Datasheet
INTEL [ INTEL ]
