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Intel Advanced+ Boot Block Flash Memory (C3)
Table 31. Device Geometry Details
16 Mbit
32 Mbit
64 Mbit
Address
-B
-T
-B
-T
-B
-T
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
--15
--01
--00
--00
--00
--02
--07
--00
--20
--00
--1E
--00
--00
--01
-15
--01
--00
--00
--00
--02
--1E
--00
--00
--01
--07
--00
--20
--00
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
-16
--01
-00
--17
--01
-00
--17
--01
-00
-00
-00
-00
-00
-00
-00
--02
--3E
-00
--02
--07
-00
--02
--7E
-00
-00
--20
--00
--7E
-00
--00
--01
--07
-00
--01
--07
-00
--20
--00
--00
--01
--20
--00
C.6
Intel-Specific Extended Query Table
Certain flash features and commands are optional. The Intel-Specific Extended Query table
specifies this and other similar types of information.
Table 32. Primary-Vendor Specific Extended Query (Sheet 1 of 2)
Offset1
P = 0x15
Description
(Optional Flash Features and Commands)
Length
Address
Hex Code
Value
0x(P+0)
0x(P+1)
0x(P+2)
35:
36:
37:
--50
--52
--49
“P”
“R”
“I”
Primary extended query table
Unique ASCII string “PRI”
3
0x(P+3)
0x(P+4)
1
1
Major version number, ASCII
Minor version number, ASCII
38:
39:
--31
--30
“1”
“0”
Optional feature and command support (1=yes,
0=no)
bits 9–31 are reserved; undefined bits are “0.” If bit
31 is “1” then another 31 bit field of optional
features follows at the end of the bit-30 field.
3A:
3B:
3C:
3D:
--66
--00
--00
--00
0x(P+5)
0x(P+6)
0x(P+7)
0x(P+8)
bit 0 Chip erase supported
bit 0 = 0
No
Yes
Yes
No
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
4
No
Yes
Yes
No
bit 7 Page mode read supported
bit 8 Synchronous read supported
No
62
Datasheet
INTEL [ INTEL ]
