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Intel Advanced+ Boot Block Flash Memory (C3)
Figure 18. Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0xC0
PR Setup Addr = First Location to Program
Write
Write
Read
Write 0xC0,
PR Address
(Program Setup)
(Confirm Data)
Protection Data = Data to Program
Program Addr = Location to Program
Write PR
Address & Data
Status Register Data. Toggle CE# or
None
OE# to Update Status Register Data
Read Status
Register
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Idle
None
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
0
SR[7] =
1
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
Bus
Operation
Command
Comments
Check SR[1], SR[3], SR[4]:
0,1,1 = VPP Range Error
Idle
Idle
Idle
None
1
SR[3], SR[4] =
0
VPP Range Error
Program Error
Check SR[1], SR[3], SR[4]:
0,0,1 = Programming Error
None
None
Check SR[1], SR[3], SR[4]:
1,0,1 = Block locked; operation aborted
1
1
SR[3], SR[4] =
SR[3] must be cleared before the Write State Machine will
allow further program attempts.
0
Only the Clear Staus Register command clears SR[1, 3, 4].
Register Locked;
Program Aborted
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
SR[3], SR[4] =
0
Program
Successful
Datasheet
57
INTEL [ INTEL ]
