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RC28F160C3TD70 参数 Datasheet PDF下载

RC28F160C3TD70图片预览
型号: RC28F160C3TD70
PDF下载: 下载PDF文件 查看货源
内容描述: 高级+引导块闪存( C3 ) [Advanced+ Boot Block Flash Memory (C3)]
分类和应用: 闪存内存集成电路
文件页数/大小: 68 页 / 1132 K
品牌: INTEL [ INTEL ]
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Intel Advanced+ Boot Block Flash Memory (C3)  
2.3  
Signal Descriptions  
Table 2 lists the active signals used and provides a brief description of each.  
Table 2. Signal Descriptions  
Symbol  
Type  
Name and Function  
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase  
cycle.  
8 Mbit: AMAX= A18  
16 Mbit: AMAX = A19  
32 Mbit: AMAX = A20  
64 Mbit: AMAX = A21  
A[MAX:0]  
DQ[15:0]  
INPUT  
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read  
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is  
OUTPUT internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are  
disabled.  
INPUT/  
CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense  
amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption  
to standby levels.  
CE#  
OE#  
INPUT  
INPUT  
OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a  
Read operation.  
RESET/DEEP POWER-DOWN: Active-low input.  
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to  
High-Z, resets the Write State Machine, and minimizes current levels (ICCD).  
RP#  
INPUT  
INPUT  
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to  
logic-high, the device resets all blocks to locked and defaults to the read array mode.  
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on  
the rising edge of the WE# pulse.  
WE#  
WRITE PROTECT: Active-low input.  
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot  
be unlocked through software.  
WP#  
INPUT  
When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are  
now locked and can be unlocked and locked through software. After WP# goes low, any blocks  
previously marked lock-down revert to the lock-down state.  
See Section 5.0, “Security Modes” on page 27 for details on block locking.  
PROGRAM/ERASE POWER SUPPLY: Operates as an input at logic levels to control complete device  
protection. Supplies power for accelerated Program and Erase operations in 12 V ± 5% range. This pin  
cannot be left floating.  
Lower VPP VPPLK to protect all contents against Program and Erase commands.  
INPUT/  
POWER  
Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can  
drop as low as 1.65 V to allow for resistor or diode drop from the system supply.  
VPP  
Apply VPP to 12 V ± 5% for faster program and erase in a production environment. Applying 12 V ± 5%  
to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the  
boot blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 5.6 for  
details on VPP voltage configurations.  
VCC  
VCCQ  
GND  
DU  
POWER DEVICE CORE POWER SUPPLY: Supplies power for device operations.  
OUTPUT POWER SUPPLY: Output-driven source voltage. This ball can be tied directly to VCC if  
operating within VCC range.  
POWER  
POWER GROUND: For all internal circuitry. All ground inputs must be connected.  
DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or  
other balls, and must be left floating.  
-
NC  
-
NO CONNECT: Pin must be left floating.  
Datasheet  
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