28F640L30, 28F128L30, 28F256L30
Figure 33. Buffered EFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
Setup Phase
Program & Verify Phase
Exit Phase
Start
Read Status Reg.
Read Status Reg.
VPP applied,
Block unlocked
No (SR[0]=1)
No (SR[7]=0)
BEFP
Exited?
Data Stream
Ready?
Yes (SR[7]=1)
Yes (SR[0]=0)
Write 0x80 @
1
ST Word Address
Initialize Count:
X = 0
Full Status Check
Procedure
Write 0xD0 @
1ST Word Address
ST
Wri te Data @ 1
Program
Word Address
Complete
BEFP setup delay
Read Status Reg.
Increment Count:
X = X+1
N
X = 32?
Yes (SR[7]=0)
BEFP Setup
Done?
Y
Read Status Reg.
No (SR[7]=1)
No (SR[0]=1)
Check VPP, Lock
Errors (SR[3,1])
Program
Done?
Exit
Yes (SR[0]=0)
N
Last
Data?
Y
Wri te 0xFFFF,
Address Not within
Current Block
BEFP Setup
BEFP Program & Verify
BEFP Exit
Bus
State
Bus
State
Operation
Comments
Bus State Operation
Comments
Operation
Status
Comments
Data = Status Reg. Data
Unlock
Block
Status
Read
Data = Status Register Data
Address = 1ST Word Addr.
Write
VPPH applied to VPP
Read
Register
Register Address = 1ST Word Addr
Write
(Note 1)
BEFP
Setup
Data = 0x80 @ 1ST Word
Address
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Check SR[7]:
Check Exit
Data Stream
Standby
Standby
0 = Exit Not Completed
Status
Ready?
1 = Exit Completed
BEFP
Confirm Address
Data = 0x80 @ 1ST Word
Write
Read
Initialize
Standby
Repeat for subsequent blocks;
X = 0
Count
Status
Data = Status Reg. Data
After BEFP exit, a full Status Register check can
determine if any program error occurred;
Register Address = 1ST Word Addr
Wri te
Load
Data = Data to Program
Address = 1ST Word Addr.
(Note 2)
Buffer
BEFP
Setup
Done?
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
See full Status Register check procedure in the
Word Program flowchart.
Standby
Increment
Count
Standby
Standby
Read
X = X+1
Write 0xFF to enter Read Array state.
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Error
If SR[7] is set, check:
Buffer
Full?
Standby Condition SR[3] set = VPP Error
Check SR[1] set = Locked Block
Status
Register
Data = Status Reg. data
Address = 1ST Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
Program
Done?
Standby
Last
Data?
No = Fill buffer again
Yes = Exit
Standby
Wri te
Exit Prog & Data = 0xFFFF @ address not in
Verify Phase current block
NOTES:
1. First-word address to be programmed within the target blocmk ust be aligned on a write-buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word addresWs;S M internally increments addressing.
Datasheet
77
INTEL [ INTEL ]
