28F640L30, 28F128L30, 28F256L30
Figure 11. Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
OE# [G]
Data [D/Q]
0x20
Valid Array Data
0xD0
Figure 12. Operating Mode with Illegal Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
Partition A
OE# [G]
Data [D/Q]
0x20
0xFF
0xD0
SR[7:0]
8.2.1
8.2.2
Simultaneous Operation Details
The L30 flash memory device supports simultaneous read from one partition while programming
or erasing in any other partition. Certain features like the Protection Registers and Query data have
special requirements with respect to simultaneous operation capability. These will be detailed in
the following sections.
Synchronous and Asynchronous Read-While-Write Characteristics
and Waveforms
This section describes the transitions of write operation to asynchronous read, and synchronous
read to write operation.
8.2.2.1
Write operation to asynchronous read transition
W18 - t
WHAV
The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a
write cycle (WE# going high) to perform an asynchronous read (only address valid is required).
W19 and W20 - t
and t
WHVH
WHCV
The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to
ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a
synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high
to latch a new address must be met.
44
Datasheet
INTEL [ INTEL ]
