LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Table 49. Interrupt Enable Register (Address 18, Hex 12) (Continued)
Bit
18.2
Name
Reserved
Description
Type 1
Default
Write as 0, ignore on read.
Interrupt Enable.
R/W
0
18.1
18.0
INTEN
TINT
R/W
R/W
0
0
1 = Enable interrupts on this port.
0 = Disable interrupts on this port.
Test Interrupt.
1 = Force interrupt on MDINT.
0 = Normal operation.
1. R/W = Read /Write.
Table 50. Interrupt Status Register (Address 19, Hex 13)
Bit
Name
Description
Type 1
Default
19.15:8 Reserved
Ignore.
RO
N/A
Auto Negotiation Status.
19.7
19.6
ANDONE
RO/SC
RO/SC
N/A
0
1= Auto Negotiation has completed.
0= Auto Negotiation has not completed.
Speed Change Status.
SPEEDCHG
1 = A Speed Change has occurred since last reading this register.
0 = A Speed Change has not occurred since last reading this register.
Duplex Change Status.
19.5
19.4
DUPLEXCHG
LINKCHG
1 = A Duplex Change has occurred since last reading this register.
0 = A Duplex Change has not occurred since last reading this register.
RO/SC
RO/SC
0
Link Status Change Status.
1 = A Link Change has occurred since last reading this register.
0 = A Link Change has not occurred since last reading this register.
0
0
19.3
Reserved
MDINT
Write as zero, ignore on read.
RO/SC
RO/SC
RO
1 = MII interrupt pending.
19.2
0 = No MII interrupt pending.
19.1:0
Reserved
Ignore.
0
1. R/O = Read Only.
SC = Self Clearing when read.
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Datasheet
INTEL [ INTEL ]
