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JS28F128P30T85 参数 Datasheet PDF下载

JS28F128P30T85图片预览
型号: JS28F128P30T85
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔的StrataFlash嵌入式存储器 [Intel StrataFlash Embedded Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 102 页 / 1616 K
品牌: INTEL [ INTEL ]
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1-Gbit P30 Family  
Table 4.  
QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)  
Symbol  
Type  
Name and Function  
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-  
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function  
enabling blocks to be erased or programmed using software commands.  
WP#  
Input  
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory  
contents cannot be altered when V V  
. Block erase and program at invalid V voltages  
PP  
PPLK  
PP  
should not be attempted.  
Set V = V for in-system program and erase operations. To accommodate resistor or diode drops  
PP  
CC  
Power/  
lnput  
VPP  
VCC  
from the system supply, the V level of V can be as low as V  
min. V must remain above V  
IH  
PP  
PPL PP PPL  
min to perform in-system flash modification. VPP may be 0 V during read operations.  
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500  
PPH  
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of  
this pin at 9 V may reduce block cycling capability.  
Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when  
Power  
V
V  
. Operations at invalid V voltages should not be attempted.  
CC  
LKO CC  
VCCQ  
VSS  
Power Output Power Supply: Output-driver source voltage.  
Power Ground: Connect to system ground. Do not float any VSS connection.  
Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These  
should be treated in the same way as a Do Not Use (DU) signal.  
RFU  
DU  
NC  
Do Not Use: Do not connect to any other signal, or power supply; must be left floating.  
No Connect: No internal connection; can be driven or floated.  
4.3  
SCSP Configurations  
Table 5.  
Stacked Easy BGA Chip Select Logic  
Selected Flash  
Selected Flash  
Die #2  
Stack Combination  
Die #1  
1-die  
2-die  
F1-CE#  
-
F1-CE# + A25 (V )  
F1-CE# + A25 (V )  
IH  
IL  
Table 6.  
QUAD+ SCSP Chip Select Logic  
Stack  
Combination  
Selected Flash  
Die #1  
Selected Flash  
Die #2  
Selected Flash  
Die #3  
Selected Flash  
Die #4  
1-die  
2-die  
4-die  
F1-CE#  
-
-
-
-
-
F1-CE# + A24 (V ) F1-CE# + A24 (V  
)
)
IL  
IH  
F1-CE# + A24 (V ) F1-CE# + A24 (V  
F2-CE# + A24 (V ) F2-CE# + A24 (V )  
IL IH  
IL  
IH  
April 2005  
22  
Intel StrataFlash® Embedded Memory (P30)  
Order Number: 306666, Revision: 001  
Datasheet  
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