Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figures
1
2
3
4
5
6
7
8
Intel® IXP425 Network Processor Block Diagram ......................................................................15
Intel® IXP423 Network Processor Block Diagram ......................................................................16
Intel® IXP422 Network Processor Block Diagram ......................................................................17
Intel® IXP421 Network Processor Block Diagram ......................................................................18
Intel® IXP420 Network Processor Block Diagram ......................................................................19
Intel XScale® Core Block Diagram .............................................................................................27
492-Pin Lead PBGA Package ....................................................................................................50
Package Markings ......................................................................................................................51
9
V
V
V
V
Power Filtering Diagram...............................................................................................83
Power Filtering Diagram...............................................................................................83
Power Filtering Diagram .............................................................................................84
CCPLL1
CCPLL2
CCOSCP
10
11
12
Power Filtering Diagram ...............................................................................................84
CCOSC
13 RCOMP Pin External Resistor Requirements ............................................................................85
14 Typical Connection to a Crystal..................................................................................................93
15 Typical Connection to an Oscillator ............................................................................................93
16 PCI Output Timing ......................................................................................................................95
17 PCI Input Timing.........................................................................................................................95
18 UTOPIA-2 Input Timings.............................................................................................................97
19 UTOPIA-2 Output Timings..........................................................................................................97
20 MII Output Timings .....................................................................................................................98
21 MII Input Timings ........................................................................................................................98
22 MDIO Output Timings.................................................................................................................99
23 MDIO Input Timings....................................................................................................................99
24 SDRAM Input Timings ..............................................................................................................100
25 SDRAM Output Timings ...........................................................................................................100
26 Signal Timing With Respect to Clock Rising Edge ...................................................................101
27 Intel® Multiplexed Read Mode ..................................................................................................102
28 Intel® Multiplexed Write Mode ..................................................................................................103
29 Intel® Simplex Read Mode........................................................................................................105
30 Intel® Simplex Write Mode........................................................................................................105
31 Motorola* Multiplexed Read Mode............................................................................................107
32 Motorola* Multiplexed Write Mode............................................................................................108
33 Motorola* Simplex Read Mode.................................................................................................110
34 Motorola* Simplex Write Mode .................................................................................................111
35 HPI-8 Mode Read Accesses.....................................................................................................113
36 HPI-8 Mode Write Accesses.....................................................................................................114
37 HPI-16 Multiplexed Write Mode................................................................................................118
38 HPI-16 Multiplex Read Mode....................................................................................................120
39 HPI-16 Simplex Read Mode .....................................................................................................122
40 HPI-16 Simplex Write Mode .....................................................................................................124
41 High-Speed, Serial Timings......................................................................................................125
42 Boundary-Scan General Timings..............................................................................................127
43 Boundary-Scan Reset Timings.................................................................................................127
44 Reset Timings...........................................................................................................................128
45 Power-Up Sequence Timing.....................................................................................................130
Datasheet
March 2005
5
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
