Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 58.
HPI Timing Symbol Description
State
T1
Description
Address Timing
Setup/Chip Select Timing
Strobe Timing
Min.
Max.
4
Unit
Notes
1, 5, 6
2, 6
3
3
2
3
2
Cycles
Cycles
Cycles
Cycles
Cycles
T2
4
T3
16
4
3, 5, 6
6
T4
Hold Timing
T5
Recovery Phase
17
6
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
5.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
6.
7.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
Table 59.
HPI-8 Mode Write Access Values
Symbol
Parameter
Min.
Max. Units
Notes
Cycles 1, 5, 6
Cycles 5, 6
Cycles 2, 4, 5
Valid time that address is asserted on the line. The
address is asserted at the same time as chip select.
Tadd_setup
11
45
Delay from chip select being active and the HDS1 data
strobe being active.
Tcs2hds1val
3
4
4
5
Thds1_pulse
Pulse width of the HDS1 data strobe
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
5.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
6.
7.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
Datasheet
March 2005
Document Number: 252479, Revision: 005
115
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