Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 2.
Terminology and Acronyms (Continued)
Acronym/
Terminology
Description
DDR
DES
DMA
DSP
E1
Double Data Rate
Data-Encryption Standard
Direct Memory Access
Digital Signal Processor
Euro 1 trunk line
FIFO
GCI
First In First Out
General Circuit Interface
General-purpose input/output
High-level Data Link Control
GPIO
HDLC
HPI
(Texas Instruments*) Host Port Interfaces
High-Speed Serial (port)
HSS
LSb
Least-Significant bit
LSB
MAC
MDIO
MII
Least-Significant Byte
Media Access Controller
Management Data Input/Output
Media-Independent Interface
Memory Management Unit
Most-Significant bit
MMU
MSb
MSB
NPE
PCI
Most-Significant Byte
Network Processor Engine
Peripheral Component Interconnect
Physical Layer (Layer 1) Interface
PHY
A field that may be used by an implementation. Software should not modify reserved fields
or depend on any values in reserved fields.
Reserved
RX
SRAM
SDRAM
T1
Receive (HSS is receiving from off-chip)
Static Random Access Memory
Synchronous Dynamic Random Access Memory
Type 1 trunk line
TX
Transmit (HSS is transmitting off-chip)
Universal Asynchronous Receiver-Transmitter
Universal Serial Bus
UART
USB
UTOPIA
WAN
Universal Test and Operations PHY Interface for ATM
Wide Area Network
March 2005
10
Datasheet
Document Number: 252479, Revision: 005
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