MAX 7000A Programmable Logic Device Data Sheet
Table 17. EPM7064AE Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7
Unit
-4
-10
Min
Max Min
Max
Min Max
tIC
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
1.2
0.6
1.0
1.3
1.3
1.0
3.5
1.9
1.0
1.5
2.1
2.1
1.7
4.0
2.5
1.2
2.2
2.9
2.9
2.3
5.0
ns
ns
ns
ns
ns
ns
ns
tEN
tGLOB
tPRE
tCLR
tPIA
(2)
(6)
tLPA
Low-power adder
Altera Corporation
35