MAX 7000A Programmable Logic Device Data Sheet
Table 16. EPM7064AE External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7
Unit
-4
-10
Min
Max
Min
Max
Min
Max
tPD1
tPD2
tSU
Input to non-
C1 = 35 pF
4.5
7.5
10.0
ns
ns
ns
registered output
(2)
I/O input to non-
registered output
C1 = 35 pF
4.5
7.5
10.0
(2)
Global clock setup
time
(2)
2.8
4.7
6.2
tH
Global clock hold time (2)
0.0
2.5
0.0
3.0
0.0
3.0
ns
ns
tFSU
Global clock setup
time of fast input
tFH
Global clock hold time
of fast input
0.0
1.0
0.0
1.0
0.0
1.0
ns
ns
tCO1
Global clock to output C1 = 35 pF
delay
3.1
4.3
5.1
7.2
7.0
9.6
tCH
Global clock high time
2.0
2.0
1.6
0.3
1.0
3.0
3.0
2.6
0.4
1.0
4.0
4.0
3.6
0.6
1.0
ns
ns
ns
ns
ns
tCL
Global clock low time
tASU
tAH
Array clock setup time (2)
Array clock hold time (2)
Array clock to output C1 = 35 pF
tACO1
delay
(2)
tACH
tACL
Array clock high time
Array clock low time
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
ns
ns
ns
tCPPW
Minimum pulse width (3)
for clear and preset
tCNT
Minimum global clock (2)
4.5
4.5
7.4
7.4
10.0
10.0
ns
MHz
ns
period
fCNT
Maximum internal
(2), (4)
222.2
222.2
135.1
135.1
100.0
100.0
global clock frequency
tACNT
fACNT
Minimum array clock (2)
period
Maximum internal
(2), (4)
MHz
array clock frequency
Altera Corporation
33
INTEL [ INTEL ]
