MAX 7000A Programmable Logic Device Data Sheet
Table 25. EPM7128A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
Min Max Min Max Min Max Min Max
tRD
Register delay
1.7
1.7
2.4
2.4
1.0
3.1
3.1
0.9
11.0
2.1
2.1
3.0
3.0
1.2
3.9
3.9
1.1
10.0
2.8
2.8
4.1
4.1
1.7
5.2
5.2
1.5
10.0
3.3
3.3
4.9
4.9
2.0
6.2
6.2
1.8
ns
ns
ns
ns
ns
ns
ns
ns
tCOMB
tIC
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
tEN
tGLOB
tPRE
tCLR
tPIA
(2)
(6)
tLPA
Low-power adder
10.0 ns
Altera Corporation
47