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EPM7256AETC100-10N 参数 Datasheet PDF下载

EPM7256AETC100-10N图片预览
型号: EPM7256AETC100-10N
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 10ns, 256-Cell, CMOS, PQFP100, TQFP-100]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 66 页 / 1120 K
品牌: INTEL [ INTEL ]
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MAX 7000A Programmable Logic Device Data Sheet  
Open-Drain Output Option  
MAX 7000A devices provide an optional open-drain (equivalent to  
open-collector) output for each I/O pin. This open-drain output enables  
the device to provide system-level control signals (e.g., interrupt and  
write enable signals) that can be asserted by any of several devices. This  
output can also provide an additional wired-ORplane.  
Open-drain output pins on MAX 7000A devices (with a pull-up resistor to  
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high  
VIH. When the open-drain pin is active, it will drive low. When the pin is  
inactive, the resistor will pull up the trace to 5.0 V to meet CMOS VOH  
requirements. The open-drain pin will only drive low or tri-state; it will  
never drive high. The rise time is dependent on the value of the pull-up  
resistor and load impedance. The IOL current specification should be  
considered when selecting a pull-up resistor.  
Programmable Ground Pins  
Each unused I/O pin on MAX 7000A devices may be used as an  
additional ground pin. In EPM7128A and EPM7256A devices, utilizing  
unused I/O pins as additional ground pins requires using the associated  
macrocell. In MAX 7000AE devices, this programmable ground feature  
does not require the use of the associated macrocell; therefore, the buried  
macrocell is still available for user logic.  
Slew-Rate Control  
The output buffer for each MAX 7000A I/O pin has an adjustable output  
slew rate that can be configured for low-noise or high-speed performance.  
A faster slew rate provides high-speed transitions for high-performance  
systems. However, these fast transitions may introduce noise transients  
into the system. A slow slew rate reduces system noise, but adds a  
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the  
slew rate is set for low-noise performance. Each I/O pin has an individual  
EEPROM bit that controls the slew rate, allowing designers to specify the  
slew rate on a pin-by-pin basis. The slew rate control affects both the rising  
and falling edges of the output signal.  
22  
Altera Corporation  
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