EPM7256AETC144-10N 参数 Datasheet PDF下载

MAX 7000A Programmable Logic Device Data Sheet

Figure 1. MAX 7000A Device Block Diagram

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 or 10 Output Enables

(1)

LAB A

36

36

6 or 10 Output Enables

(1)

LAB B

2 to 16

2 to 16

2 to 16 I/O

2 to 16

I/O

Control

Block

Macrocells

1 to 16

16

Macrocells

17 to 32

2 to 16

I/O

Control

Block

2 to 16 I/O

16

6

2 to 16

2 to 16

2 to 16

6

LAB C

PIA

Macrocells

33 to 48

16

36

36

LAB D

2 to 16

2 to 16 I/O

I/O

Control

Block

2 to 16

Macrocells

49 to 64

2 to 16

I/O

Control

Block

2 to 16 I/O

16

6

2 to 16

2 to 16

6

Note:

(1)

EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.

EPM7512AE devices have 10 output enables.

Logic Array Blocks

The MAX 7000A device architecture is based on the linking of

high-performance LABs. LABs consist of 16-macrocell arrays, as shown in

Figure 1.

Multiple LABs are linked together via the PIA, a global bus that

is fed by all dedicated input pins, I/O pins, and macrocells.

Each LAB is fed by the following signals:

■

■

■

36 signals from the PIA that are used for general logic inputs

Global controls that are used for secondary register functions

Direct input paths from I/O pins to the registers that are used for fast

setup times

Altera Corporation

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