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EPM3064ATC44-4NAG 参数 Datasheet PDF下载

EPM3064ATC44-4NAG图片预览
型号: EPM3064ATC44-4NAG
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 4.5ns, CMOS, PQFP44, TQFP-44]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 46 页 / 709 K
品牌: INTEL [ INTEL CORPORATION ]
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MAX 3000A Programmable Logic Device Family Data Sheet
Figure 4. MAX 3000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
From
Previous
Macrocell
Preset
Product-
er
Select
Matrix
Clock
Clear
Macrocell
Product-
Term Logic
Preset
Product-
T
Term
Select
Matrix
Clock
Clear
Macrocell
Product-
Term Logic
36 Signals
from PIA
16 Shared
Expanders
To Next
Macrocell
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 3000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB.
shows how the PIA signals are routed
into the LAB. An EEPROM cell controls one input to a two-input
AND
gate,
which selects a PIA signal to drive into the LAB.
10
Altera Corporation