MAX 3000A Programmable Logic Device Family Data Sheet
Table 24. EPM3512A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
Min
Max
Min
Max
tAH
tACO1
tACH
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
(2)
C1 = 35 pF (2)
0.2
1.0
3.0
3.0
3.0
0.3
1.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
7.8
10.4
tACL
tCPPW
Minimum pulse width for clear (3)
and preset
tCNT
fCNT
Minimum global clock period
(2)
8.6
8.6
11.5
11.5
ns
Maximum internal global clock (2), (4)
frequency
116.3
116.3
87.0
87.0
MHz
tACNT
fACNT
Minimum array clock period
(2)
ns
Maximum internal array clock (2), (4)
MHz
frequency
Table 25. EPM3512A Internal Timing Parameters (Part 1 of 2)
Note (1)
Speed Grade
Symbol
Parameter
Conditions
Unit
-7
-10
Min
Max
Min
Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.7
0.7
3.1
2.7
0.4
2.2
1.0
0.0
1.0
0.9
0.9
3.6
3.5
0.5
2.8
1.3
0.0
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
tOD1
Output buffer and pad delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
C1 = 35 pF
tOD2
Output buffer and pad delay,
slow slew rate = off
VCCIO = 2.5 V
1.5
2.0
ns
Altera Corporation
37
INTEL [ INTEL ]
