Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
4–7
Power-On Reset Circuitry
Figure 4–5. Power-Up Characteristics for MAX II, MAX IIG, and MAX IIZ Devices (Note 1), (2)
MAX II Device
V
3.3 V
2.5 V
CCINT
Approximate Voltage
for SRAM Download Start
Device Resets
the SRAM and
Tri-States I/O Pins
1.7 V
1.4 V
t
CONFIG
0 V
User Mode
Operation
Tri-State
Tri-State
Tri-State
Tri-State
MAX IIG Device
V
CCINT
3.3 V
Approximate Voltage
for SRAM Download Start
Device Resets
the SRAM and
Tri-States I/O Pins
1.8 V
1.55 V
1.4 V
t
CONFIG
0 V
User Mode
Operation
Tri-State
MAX IIZ Device
V
CCINT
3.3 V
V
must be powered down
to 0 V if the V
dips below this level
CCINT
Approximate Voltage
for SRAM Download Start
CCINT
1.8 V
1.55 V
1.4 V
t
minimum 10 µs
t
CONFIG
CONFIG
0 V
User Mode
Operation
User Mode
Operation
Tri-State
Notes to Figure 4–5:
(1) Time scale is relative.
(2) Figure 4–5 assumes all VCCIO banks power up simultaneously with the VCCINT profile shown. If not, tCONFIG stretches out until all VCCIO banks are powered.
1
After SRAM configuration, all registers in the device are cleared and released into
user function before I/O tri-states are released. To release clears after tri-states are
released, use the DEV_CLRnpin option. To hold the tri-states beyond the power-up
configuration time, use the DEV_OE pin option.
© October 2008 Altera Corporation
MAX II Device Handbook
INTEL [ INTEL ]
