Chapter 5: DC and Switching Characteristics
5–11
Timing Model and Specifications
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device
density. Table 5–15 through Table 5–22 describe the MAX II device internal timing
microparameters for logic elements (LEs), input/output elements (IOEs), UFM
blocks, and MultiTrack interconnects. The timing values for –3, –4, and –5 speed
grades shown in Table 5–15 through Table 5–22 are based on an EPM1270 device
target, while –6, –7, and –8 speed grade values are based on an EPM570Z device
target.
f
For more explanations and descriptions about each internal timing microparameters
symbol, refer to the Understanding Timing in MAX II Devices chapter in the MAX II
Device Handbook.
Table 5–15. LE Internal Timing Microparameters
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Unit
tLUT
LE combinational
LUT delay
—
571
147
—
—
742
192
—
—
914
236
—
—
1,215
243
—
—
2,247
305
—
—
2,247 ps
tCOMB
tCLR
tPRE
tSU
Combinational
path delay
—
—
—
—
—
—
309
—
ps
ps
ps
ps
ps
ps
ps
LE register clear
delay
238
238
208
0
309
309
271
0
381
381
333
0
401
401
260
0
541
541
319
0
545
545
321
0
LE register preset
delay
—
—
—
—
—
—
LE register setup
time before clock
—
—
—
—
—
—
tH
LE register hold
time after clock
—
—
—
—
—
—
tCO
LE register clock-
to-output delay
—
235
—
—
305
—
—
376
—
—
380
—
—
489
—
—
494
—
tCLKHL
tC
Minimum clock
high or low time
166
—
216
—
266
—
253
—
335
—
339
—
Register control
delay
857
1,114
1,372
1,356
1,722
1,741 ps
© August 2009 Altera Corporation
MAX II Device Handbook
INTEL [ INTEL ]
