5–16
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 3 of 3)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol
tOE
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Delay from data
register clock to data
register output
180
—
180
—
180
—
180
—
180
—
180
—
ns
tRA
Maximum read
access time
—
65
—
—
65
—
—
65
—
—
65
—
—
65
—
—
65
—
ns
ns
tOSCS
Maximum delay
between the
250
250
250
250
250
250
OSC_ENArising
edge to the
erase/program signal
rising edge
tOSCH
Minimum delay
allowed from the
erase/program signal
going low to
250
—
250
—
250
—
250
—
250
—
250
—
ns
OSC_ENAsignal
going low
Figure 5–3 through Figure 5–5 show the read, program, and erase waveforms for
UFM block timing parameters shown in Table 5–21.
Figure 5–3. UFM Read Waveforms
ARShft
tAH
9 Address Bits
tACLK
tASU
ARClk
ARDin
DRShft
DRClk
tADH
tADS
16 Data Bits
tDSH
tDCLK
tDSS
tDCO
DRDin
DRDout
OSC_ENA
Program
Erase
Busy
MAX II Device Handbook
© August 2009 Altera Corporation