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EPM1270F256C5N 参数 Datasheet PDF下载

EPM1270F256C5N图片预览
型号: EPM1270F256C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 10ns, 980-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
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5–2  
Chapter 5: DC and Switching Characteristics  
Operating Conditions  
Recommended Operating Conditions  
Table 5–2 shows the MAX II device family recommended operating conditions.  
Table 5–2. MAX II Device Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
MAX II devices  
Minimum  
Maximum  
Unit  
V
V
CCINT (1)  
3.3-V supply voltage for internal logic and  
ISP  
3.00  
3.60  
V
2.5-V supply voltage for internal logic and  
ISP  
MAX II devices  
2.375  
1.71  
2.625  
1.89  
V
V
V
V
V
V
1.8-V supply voltage for internal logic and  
ISP  
MAX IIG and MAX IIZ  
devices  
CCIO (1)  
Supply voltage for I/O buffers, 3.3-V  
operation  
3.00  
3.60  
Supply voltage for I/O buffers, 2.5-V  
operation  
2.375  
1.71  
2.625  
1.89  
Supply voltage for I/O buffers, 1.8-V  
operation  
Supply voltage for I/O buffers, 1.5-V  
operation  
1.425  
1.575  
VI  
VO  
TJ  
Input voltage  
(2), (3), (4)  
–0.5  
0
4.0  
VCCIO  
85  
V
V
Output voltage  
Operating junction temperature  
Commercial range  
Industrial range  
Extended range (5)  
0
°C  
°C  
°C  
–40  
–40  
100  
125  
Notes to Table 5–2:  
(1) MAX II device in-system programming and/or user flash memory (UFM) programming via JTAG or logic array is not guaranteed outside the  
recommended operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM,  
users are recommended to read back UFM contents and verify against the intended write data).  
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter  
than 20 ns.  
(3) During transitions, the inputs may overshoot to the voltages shown in the following table based upon input duty cycle. The DC case is equivalent  
to 100% duty cycle. For more information about 5.0-V tolerance, refer to the Using MAX II Devices in Multi-Voltage Systems chapter in the  
MAX II Device Handbook.  
VIN  
Max. Duty Cycle  
4.0 V 100% (DC)  
4.1  
4.2  
4.3  
4.4  
4.5  
90%  
50%  
30%  
17%  
10%  
(4) All pins, including clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered.  
(5) For the extended temperature range of 100 to 125º C, MAX II UFM programming (erase/write) is only supported via the JTAG interface. UFM  
programming via the logic array interface is not guaranteed in this range.  
MAX II Device Handbook  
© August 2009 Altera Corporation