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EPM1270GM100I5ES 参数 Datasheet PDF下载

EPM1270GM100I5ES图片预览
型号: EPM1270GM100I5ES
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, PBGA100, 6 X 6 MM, 0.50 MM PITCH, MICRO, FBGA-100]
分类和应用:
文件页数/大小: 98 页 / 1060 K
品牌: INTEL [ INTEL CORPORATION ]
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Chapter 4. Hot Socketing &
Power-On Reset in MAX II
Devices
MII51004-1.4
Hot Socketing
MAX
®
II devices offer hot socketing, also known as hot plug-in or hot
swap, and power sequencing support. Designers can insert or remove a
MAX II board in a system during operation without undesirable effects to
the system bus. The hot socketing feature removes some of the difficulty
designers face when using components on printed circuit boards (PCBs)
that contain a mixture of 3.3-, 2.5-, 1.8-, and 1.5-V devices.
The MAX II device hot socketing feature provides:
Board or device insertion and removal
Support for any power-up sequence
Non-intrusive I/O buffers to system buses during hot insertion
MAX II Hot-Socketing Specifications
MAX II devices offer all three of the features required for hot socketing
capability listed above without any external components or special
design requirements. The following are hot-socketing specifications:
The device can be driven before and during power-up or power-
down without any damage to the device itself.
I/O pins remain tri-stated during power-up. The device does not
drive out before or during power-up, thereby affecting other buses in
operation.
Signal pins do not drive the V
CCIO
or V
CCINT
power supplies. External
input signals to device I/O pins do not power the device V
CCIO
or
V
CCINT
power supplies via internal paths. This is true for all device
I/O pins only if V
CCINT
is held at
GND.
This is true for a particular I/O
bank if the V
CCIO
supply for that bank is held at
GND.
Devices Can Be Driven before Power-Up
Signals can be driven into the MAX II device I/O pins and
GCLK[3..0]
pins before or during power-up or power-down without damaging the
device. MAX II devices support any power-up or power-down sequence
(V
CCIO1
, V
CCIO2
, V
CCIO3
, V
CCIO4
, V
CCINT
), simplifying system-level design.
Altera Corporation
February 2006
Core Version a.b.c variable
4–1
Preliminary