Section I. MAX II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
MAX
®
II devices. The chapters contain feature definitions of the internal
architecture, Joint Test Action Group (JTAG) and in-system
programmability (ISP) information, DC operating conditions, AC timing
parameters, and ordering information for MAX II devices.
This section includes the following chapters:
■
■
■
■
■
■
Chapter 1. Introduction
Chapter 2. MAX II Architecture
Chapter 3. JTAG & In-System Programmability
Chapter 4. Hot Socketing & Power-On Reset in MAX II Devices
Chapter 5. DC & Switching Characteristics
Chapter 6. Reference & Ordering Information
Revision History
The table below shows the revision history for
Chapter(s)
1
Date/Version
August 2006, v1.5
July 2006, v1.4
June 2005, v1.3
Changes Made
Minor update to features list.
Minor updates to tables.
Updated timing numbers in Table 1-1.
December 2004, v1.2 Updated timing numbers in Table 1-1.
June 2004, v1.1
2
August 2006, v1.6
Updated timing numbers in Table 1-1.
Updated functional description and I/O
structure sections.
Altera Corporation
Section I–1
Preliminary
INTEL [ INTEL CORPORATION ]
