Timing Model & Specifications
Table 5–32. MAX II Maximum Input Clock Rate for I/O (Part 2 of 2)
Standard
-3 Speed Grade -4 Speed Grade -5 Speed Grade Unit
2.5-V LVTTL
Without Schmitt
220
220
220
MHz
Trigger
With Schmitt Trigger
188
220
188
220
188
220
MHz
MHz
2.5-V LVCMOS
Without Schmitt
Trigger
With Schmitt Trigger
188
200
188
200
188
200
MHz
MHz
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V PCI
Without Schmitt
Trigger
Without Schmitt
Trigger
200
150
304
200
150
304
200
150
304
MHz
MHz
MHz
Without Schmitt
Trigger
Without Schmitt
Trigger
Table 5–33. MAX II Maximum Output Clock Rate for I/O
Standard
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
3.3-V LVTTL
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V PCI
5–28
Core Version a.b.c variable
Altera Corporation
July 2006
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
