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EPF10K20RC208-4 参数 Datasheet PDF下载

EPF10K20RC208-4图片预览
型号: EPF10K20RC208-4
PDF下载: 下载PDF文件 查看货源
内容描述: [Loadable PLD, 0.6ns, CMOS, PQFP208, RQFP-208]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 143 页 / 1990 K
品牌: INTEL [ INTEL ]
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FLEX 10K Embedded Programmable Logic Device Family Data Sheet  
Flexible interconnect  
FastTrack® Interconnect continuous routing structure for fast,  
predictable interconnect delays  
Dedicated carry chain that implements arithmetic functions such  
as fast adders, counters, and comparators (automatically used by  
software tools and megafunctions)  
Dedicated cascade chain that implements high-speed,  
high-fan-in logic functions (automatically used by software tools  
and megafunctions)  
Tri-state emulation that implements internal tri-state buses  
Up to six global clock signals and four global clear signals  
Powerful I/ O pins  
Individual tri-state output enable control for each pin  
Open-drain option on each I/ O pin  
Programmable output slew-rate control to reduce switching  
noise  
FLEX 10KA devices support hot-socketing  
Peripheral register for fast setup and clock-to-output delay  
Flexible package options  
Available in a variety of packages with 84 to 600 pins (see  
Tables 4 and 5)  
Pin-compatibility with other FLEX 10K devices in the same  
package  
FineLine BGATM packages maximize board space efficiency  
Software design support and automatic place-and-route provided by  
Altera development systems for Windows-based PCs and Sun  
SPARCstation, HP 9000 Series 700/ 800 workstations  
Additional design entry and simulation support provided by EDIF  
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),  
DesignWare components, Verilog HDL, VHDL, and other interfaces  
to popular EDA tools from manufacturers such as Cadence,  
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,  
VeriBest, and Viewlogic  
Altera Corporation  
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