EP3C40F484C6N 参数 Datasheet PDF下载

型号：	EP3C40F484C6N
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 39600 CLBs, 472.5MHz, 39600-Cell, CMOS, PBGA484, 23 X 23 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484]
分类和应用：	时钟栅可编程逻辑
文件页数/大小：	34 页 / 836 K
品牌：	INTEL [ INTEL ]

Chapter 1: Cyclone III Device Datasheet

1–13

Electrical Characteristics

(1)

Table 1–18. Cyclone III Devices Differential I/O Standard Specifications

(Part 2 of 2)

V_OD(mV)

(2)

(3)

V_CCIO(V)

V_ID(mV)

V_IcM(V)

V_OS(V)

I/O

Standard

Min Typ Max

Min Max Min

Condition

Max Min Typ Max Min Typ Max

0.05

D_MAX 500 Mbps 1.80

LVDS

(Column

I/Os)

500 Mbps  D_MAX

 700 Mbps

2.375 2.5 2.625 100

—

0.55

1.05

1.80 247

1.55

—

600 1.125 1.25 1.375

D_MAX> 700 Mbps

BLVDS

(Row I/Os) 2.375 2.5 2.625 100

—

(5)

BLVDS

(Column

2.375 2.5 2.625 100

—

(5)

I/Os)

mini-LVDS

(Row I/Os) 2.375 2.5 2.625

—

300

600

1.0

0.5

1.2

1.4

1.5

1.4

(6)

mini-LVDS

(Column

2.375 2.5 2.625

—

(6)

I/Os)

RSDS^®

(Row

100 200 600

I/Os) ⁽⁶⁾

RSDS

(Column

(6)

I/Os)

PPDS^®

(Row I/Os) 2.375 2.5 2.625

(6)

PPDS

(Column

2.375 2.5 2.625

(6)

I/Os)

Notes to Table 1–18:

(1) For an explanation of terms used in Table 1–18, refer to “Transmitter Output Waveform” in “Glossary” on page 1–27.

(2) V_INrange: 0 V  V_IN 1.85 V.

(3) R_Lrange: 90  R_L 110  .

(4) LVPECL input standard is only supported at clock input. Output standard is not supported.

(5) No fixed V_IN, V_OD, and V_OSspecifications for BLVDS. They are dependent on the system topology.

(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 2

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