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EP3C16U256C6N 参数 Datasheet PDF下载

EP3C16U256C6N图片预览
型号: EP3C16U256C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PBGA256, 14 X 14 MM, 2.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, UFBGA-256]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone III Device Datasheet  
1–33  
Document Revision History  
Table 1–40. Document Revision History (Part 2 of 3)  
Date  
Version  
Changes  
Updated “Operating Conditions” section and included information on automotive device.  
Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive information.  
Under “Pin Capacitance” section, updated Table 1–9 and Table 1–10.  
Added new “Schmitt Trigger Input” section with Table 1–12.  
Under “I/O Standard Specifications” section, updated Table 1–13, 1–12 and 1–12.  
May 2008  
2.0  
Under “Switching Characteristics” section, updated Table 1–19, 1–15, 1–16, 1–16, 1–17,  
1–18, 1–19, 1–20, 1–21, 1–21, 1–23, 1–23, 1–23, 1–24, and 1–25.  
Updated Figure 1–5 and 1–29.  
Deleted previous Table 1-35 “DDIO Outputs Half-Period Jitter”.  
Under “I/O Timing” section, updated Table 1–38, 1–29, 1–32, 1–33, 1–26, and 1–26.  
Under “Typical Design Performance” section updated Table 1–46 through 1–145.  
Under “Core Performance Specifications”, updated Tables 1-18 and 1-19.  
Under “Preliminary, Correlated, and Final Timing”, updated Table 1-37.  
December 2007  
1.5  
Under “Typical Design Performance”, updated Tables 1-45, 1-46, 1-51, 1-52, 1-57, 1-58,  
Tables 1-63 through 1-68. 1-69, 1-70, 1-75, 1-76, 1-81, 1-82, Tables 1-87 through 1-92,  
Tables 1-99, 1-100, 1-107, and 1-108.  
Updated the CVREFTB value in Table 1-9.  
Updated Table 1-21.  
Under “High-Speed I/O Specification” section, updated Tables 1-25 through 1-30.  
Updated Tables 1-31 through 1-38.  
Added new Table 1-32.  
October 2007  
1.4  
Under “Maximum Input and Output Clock Toggle Rate” section, updated Tables 1-40  
through 1-42.  
Under “IOE Programmable Delay” section, updated Tables 1-43 through 1-44.  
Under “User I/O Pin Timing Parameters” section, updated Tables 1-45 through 1-92.  
Under “Dedicated Clock Pin Timing Parameters” section, updated Tables 1-93 through 1-  
108.  
Updated Table 1-1 with VESDHBM and VESDCDM information.  
Updated RCONF_PD information in Tables 1-10.  
Added Note (3) to Table 1-12.  
July 2007  
June 2007  
1.3  
1.2  
Updated tDLOCK information in Table 1-19.  
Updated Table 1-43 and Table 1-44.  
Added “Document Revision History” section.  
Updated Cyclone III graphic in cover page.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
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