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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone III Device Datasheet  
1–7  
Electrical Characteristics  
The OCT resistance may vary with the variation of temperature and voltage after  
calibration at device power-up. Use Table 1–8 and Equation 1–1 to determine the final  
OCT resistance considering the variations after calibration at device power-up.  
Table 1–8 lists the change percentage of the OCT resistance with voltage and  
temperature.  
Table 1–8. Cyclone III Devices OCT Variation After Calibration at Device Power-Up  
Nominal Voltage  
dR/dT (%/°C)  
0.262  
dR/dV (%/mV)  
–0.026  
3.0  
2.5  
1.8  
1.5  
1.2  
0.234  
–0.039  
0.219  
–0.086  
0.199  
–0.136  
0.161  
–0.288  
(1), (2), (3), (4), (5), (6)  
Equation 1–1.  
(7)  
RV = (V2 – V1) × 1000 × dR/dV  
(8)  
RT = (T2 – T1) × dR/dT  
(9)  
For Rx < 0; MFx = 1/ (|Rx|/100 + 1)  
(10)  
For Rx > 0; MFx = Rx/100 + 1  
(11)  
MF = MFV × MFT  
(12)  
Rfinal = Rinitial × MF  
Notes to Equation 1–1:  
(1) T2 is the final temperature.  
(2) T1 is the initial temperature.  
(3) MF is multiplication factor.  
(4) Rfinal is final resistance.  
(5) Rinitial is initial resistance.  
(6) Subscript × refers to both V and T.  
(7) RV is variation of resistance with voltage.  
(8) RT is variation of resistance with temperature.  
(9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up.  
(10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up.  
(11) V2 is final voltage.  
(12) V1 is the initial voltage.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
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